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MAX 9000
(R)
Programmable Logic Device Family
Data Sheet
December 2002, ver. 6.4
%
Usable gates Flipflops Macrocells Logic array blocks (LABs) Maximum user I/O pins tPD1 (ns) tFSU (ns) tFCO (ns) fCNT (MHz)
6,000 484 320 20 168 10 3.0 4.5 144
8,000 580 400 25 159 15 5 7 118
10,000 676 480 30 175 10 3.0 4.8 144
12,000 772 560 35 216 10 3.0 4.8 144
Altera Corporation
1
MAX 9000 Programmable Logic Device Family Data Sheet
EPM9320 EPM9320A EPM9400 EPM9480 EPM9560 EPM9560A
60 (2) 60 (2) 59 (2) - - -
132 132 139 146 153 153
- - 159 175 191 191
168 - - - 216 -
- - - - 216 -
168 168 - - 216 216
2
Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet
EPM9320 EPM9320A EPM9400 EPM9480 EPM9560 EPM9560A
16-bit loadable counter 16-bit up/down counter 16-bit prescaled counter 16-bit address decode 16-to-1 multiplexer
16 16 16 1 1
144 144 144 5.6 (10) 7.7 (12.1)
118 118 118 7.9 (15) 10.9 (18)
100 100 100 10 (20) 16 (26)
MHz MHz MHz ns ns
Altera Corporation
3
MAX 9000 Programmable Logic Device Family Data Sheet
%
4
Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet
Altera Corporation
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MAX 9000 Programmable Logic Device Family Data Sheet
IOC
IOC
IOC
IOC
IOC
IOC
IOC
IOC
IOC
IOC
IOC
IOC
IOC
IOC
IOC
IOC
6
Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet
DIN1
GCLK1
GCLK2 DIN2 DIN3 GCLR
To Peripheral Bus and Other LABs in the Device
DIN4
GOE
To Peripheral Bus
33
16
16
Macrocell 1 Macrocell 2 Macrocell 3 Macrocell 4 Macrocell 5 Macrocell 6 Macrocell 7 Macrocell 8 Macrocell 9 Macrocell 10 Macrocell 11 Macrocell 12 Macrocell 13 Macrocell 14 Macrocell 15 Macrocell 16
16 16
16
48
16
48
Altera Corporation
7
MAX 9000 Programmable Logic Device Family Data Sheet
LAB Local Array
Global Clear Global Clocks 2
Parallel Expanders (from Other Macrocells)
ProductTerm Select Matrix
Clock/ Enable Select
VCC
PRN D/T Q ENA CLRN
To Row or Column FastTrack Interconnect
Clear Select
Local Array Feedback
16 Local Feedbacks
16 Shareable Expander Product
8
Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet
Altera Corporation
9
MAX 9000 Programmable Logic Device Family Data Sheet
16 Local Feedbacks
16 Shared Expanders
10
Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet
From Previous Macrocell
Preset ProductTerm Select Matrix Clock Clear
Preset ProductTerm Select Matrix Clock Clear
16 Local Feedbacks
16 Shared Expanders
To Next Macrocell
Altera Corporation
11
MAX 9000 Programmable Logic Device Family Data Sheet
12
Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet
IOC1
IOC10
IOC1
IOC10
IOC1
IOC1
IOC8
IOC8
LAB A1
IOC1
LAB A2
IOC1
IOC8
IOC8
LAB B1
LAB B2
IOC1
IOC10
IOC1
IOC10
EPM9320, EPM9320A EPM9400 EPM9480 EPM9560, EPM9560A
4 5 6 7
5 5 5 5
Altera Corporation
13
MAX 9000 Programmable Logic Device Family Data Sheet
LAB Macrocell 1
Macrocell 2
To LAB Local Array
14
Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet
10
IOC1
Row FastTrack Interconnect
96
96
96 10 IOC8
Altera Corporation
15
MAX 9000 Programmable Logic Device Family Data Sheet
IOC1
IOC10
17 48 48 48
17
Column FastTrack Interconnect
16
Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet
Peripheral Control Bus [12..0]
VCC OE [7..0] 8
To Row or Column FastTrack Interconnect From Row or Column FastTrack Interconnect
13
D CLK [3..0] 4 VCC ENA [5..0] 6 CLR [1..0] 2 VCC
Q
ENA CLRN
Slew-Rate Control
Altera Corporation
17
MAX 9000 Programmable Logic Device Family Data Sheet
Row C Row B Row A Row B Row A Row D Row C Row B/ Row A/
Row E Row E Row E Row B Row A Row D Row C Row B/ Row A/
Row F Row F Row E Row B Row A Row D Row C Row B/ Row A/
Row G Row F Row E Row B Row A Row D Row C Row B/ Row A/
Row D Row C
Row D Row C
Row D Row C
Row D Row C
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Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet
Altera Corporation
19
MAX 9000 Programmable Logic Device Family Data Sheet
SAMPLE/PRELOAD Allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern output at the device pins. EXTEST BYPASS Allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. and pins, which allows the BST Places the 1-bit bypass register between the data to pass synchronously through a selected device to adjacent devices during normal device operation. Selects the IDCODE register and places it between and , allowing the IDCODE to be shifted out of . Supported by the EPM9320A, EPM9400, EPM9480, and EPM9560A devices only. Selects the user electronic signature (UESCODE) register and allows the UESCODE to be shifted out of serially. This instruction is supported by MAX 9000A devices only. These instructions are used when programming MAX 9000 devices via the JTAG ports with the BitBlaster or ByteBlasterMV download cable, or using a Jam File (.jam), Jam Byte-Code File (.jbc), or Serial Vector Format (.svf) File via an embedded processor or test equipment.
IDCODE
UESCODE ISP Instructions
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Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet
EPM9320, EPM9320A EPM9400 EPM9480 EPM9560, EPM9560A
504 552 600 648
EPM9320A (3) EPM9400 EPM9480 EPM9560A (3)
Altera Corporation
21
MAX 9000 Programmable Logic Device Family Data Sheet
TMS
TDI
tJCP tJCH tJCL tJPSU tJPH
TCK
tJPZX tJPXZ
tJPCO
TDO
tJSSU tJSH
Signal to Be Captured Signal to Be Driven
tJSZX
tJSCO
tJSXZ
tJCP tJCH tJCL tJPSU tJPH tJPCO tJPZX tJPXZ tJSSU tJSH tJSCO tJSZX tJSXZ
clock period clock high time clock low time JTAG port setup time JTAG port hold time JTAG port clock to output JTAG port high impedance to valid output JTAG port valid output to high impedance Capture register setup time Capture register hold time Update register clock to output Update register high impedance to valid output Update register valid output to high impedance
100 50 50 20 45 25 25 25 20 45 25 25 25
ns ns ns ns ns ns ns ns ns ns ns ns ns
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Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet
%
%
VCC 464 (703 Device Output
) To Test System
250 (8.06 K ) Device input rise and fall times < 3 ns
C1 (includes JIG capacitance)
Altera Corporation
23
MAX 9000 Programmable Logic Device Family Data Sheet
VCC VI VCCISP IOUT TSTG TAMB TJ
Supply voltage DC input voltage Supply voltage during in-system programming DC output current, per pin Storage temperature Ambient temperature Junction temperature
With respect to ground (2)
-2.0 -2.0 -2.0 -25
7.0 7.0 7.0 25 150 135 150 135
V V V mA C C C C
No bias Under bias Ceramic packages, under bias PQFP and RQFP packages, under bias
-65 -65
V CCINT VCCI O
Supply voltage for internal logic and input buffers Supply voltage for output drivers, 5.0-V operation Supply voltage for output drivers, 3.3-V operation
(3), (4) (3), (4) (3), (4)
4.75 (4.50) 4.75 (4.50) 3.00 (3.00) 4.75 -0.5 0
5.25 (5.50) 5.25 (5.50) 3.60 (3.60) 5.25 V CCINT + 0.5 V CCIO 70 85 90 105 40 40
V V V V V V C C C C ns ns
VCCISP VI VO TA TJ tR tF
Supply voltage during in-system programming Input voltage Output voltage Ambient temperature Junction temperature Input rise time Input fall time For commercial use For industrial use For commercial use For industrial use
0 -40 0 -40
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Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet
V IH V IL V OH
High-level input voltage Low-level input voltage 5.0-V high-level TTL output voltage 3.3-V high-level TTL output voltage 3.3-V high-level CMOS output voltage
(7)
2.0 -0.5
V CCINT + 0.5 0.8
V V V V V
I OH = -4 mA DC, VCCIO = 4.75 V (8) I OH = -4 mA DC, VCCIO = 3.00 V (8) I OH = -0.1 mA DC, V CCIO = 3.00 V (8) I OL = 12 mA DC, VCCIO = 4.75 V (8) I OL = 12 mA DC, VCCIO = 3.00 V (8) I OL = 0.1 mA DC, VCCIO = 3.00 V (8)
2.4 2.4 VCCIO - 0.2 0.45 0.45 0.2 -10 -40 10 40
V OL
5.0-V low level TTL output voltage 3.3-V low-level TTL output voltage 3.3-V low-level CMOS output voltage
V V V A A
II I OZ
I/O pin leakage current of dedicated input VI = -0.5 to 5.5 V (9) pins Tri-state output off-state current VI = -0.5 to 5.5 V
C DIN1 C DIN2 C DIN3 C DIN4 C I/O
Dedicated input capacitance Dedicated input capacitance Dedicated input capacitance Dedicated input capacitance I/O pin capacitance
V IN = 0 V, f = 1.0 MHz V IN = 0 V, f = 1.0 MHz V IN = 0 V, f = 1.0 MHz V IN = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz
18 18 17 20 12
pF pF pF pF pF
C DIN1 C DIN2 C DIN3 C DIN4 C I/O
Dedicated input capacitance Dedicated input capacitance Dedicated input capacitance Dedicated input capacitance I/O pin capacitance
V IN = 0 V, f = 1.0 MHz V IN = 0 V, f = 1.0 MHz V IN = 0 V, f = 1.0 MHz V IN = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz
16 10 10 12 8
pF pF pF pF pF
I CC1
I CC supply current (low-power mode, standby, typical)
VI = ground, no load (11)
106
132
140
146
mA
Altera Corporation
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MAX 9000 Programmable Logic Device Family Data Sheet
I CC1
I CC supply current (low-power mode, standby, typical)
VI = ground, no load (11)
99
174
mA
%
5.0-V
150
3.3-V
IOL
150
IOL
120
120
Typical IO 90 Output Current (mA)
60
VCCIO = 5.0 V Room Temperature
Typical IO 90 Output Current (mA)
60
VCCIO = 3.3 V Room Temperature
IOH
30 30
IOH
1
2
3
4
5
1
2
3 3.3
4
5
Output Voltage (V)
Output Voltage (V)
26
Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet
Altera Corporation
27
28
tROW
Macrocell IOC
Output Data Delay tIODR tIODC FastTrack Drive Delay tFTD tCOL I/O Cell Control Delay tIOC Input Delay tINREG tINCOMB I/O Register Feedback Delay tIOFD I/O Register Delays Output Delays Parallel Expander Delay tPEXP Macrocell/ Register Delays
Logic Array Delay
tLAD
I/O Pin
Register Control Delay tLAC tIC tEN
tIORD tIOCOMB tIOSU tIOH tIOCLR
MAX 9000 Programmable Logic Device Family Data Sheet
tLOCAL
tRD tCOMB tSU tH tPRE tCLR
tOD1 tOD2 tOD3 tXZ tZX1 tZX2 tZX3
Shared Expander Delay
tSEXP
Global Input Delays
tDIN_D
tDIN_CLK
tDIN_CLR
tDIN_IO
Altera Corporation
tDIN_IOC
MAX 9000 Programmable Logic Device Family Data Sheet
tPD1 tPD2
Row I/O pin input to row I/O pin output Column I/O pin input to column I/O pin output
C1 = 35 pF (2) C1 = 35 pF EPM9320A (2) EPM9320 EPM9400 EPM9480 EPM9560A EPM9560
10.0 10.8
15.0
20.0
ns ns
16.0 16.2 16.4 11.4 16.6 3.0 0.0 5.0 0.0 4.8 6.9 144.9 117.6 1.0 (3) 7.0 8.5 100.0 6.0 0.0 1.0 (3)
23.0 23.2 23.4 23.6
ns ns ns ns ns ns ns
tFSU t FH t FCO t CNT fCNT
Global clock setup time for I/O cell Global clock hold time for I/O cell Global clock to I/O cell output delay C1 = 35 pF
1.0 (3)
8.5 10.0
ns ns MHz
Minimum internal global clock (4) period Maximum internal global clock (4) frequency
Altera Corporation
29
MAX 9000 Programmable Logic Device Family Data Sheet
t LAD t LAC tIC t EN t SEXP t PEXP t RD t COMB t SU tH t PRE t CLR t FTD t LPA
Logic array delay Logic control array delay Array clock delay Register enable time Shared expander delay Parallel expander delay Register delay Combinatorial delay Register setup time Register hold time Register preset time Register clear time FastTrack drive delay Low-power adder (5) 2.4 2.0
3.5 3.5 3.5 3.5 3.5 0.5 0.5 0.4 3.0 3.5 3.5 3.7 0.5 10.0
4.0 4.0 4.0 4.0 5.0 1.0 1.0 1.0 4.0 4.5 4.0 4.0 1.0 15.0
4.5 4.5 4.5 4.5 7.5 2.0 1.0 1.0
ns ns ns ns ns ns ns ns ns ns
4.5 4.5 2.0 20.0
ns ns ns ns
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Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet
t I ODR t I ODC t I OC t I ORD t I OCOMB t I OSU t I OH t I OCLR t I OFD t I NREG t I NCOMB t OD1
I/O row output data delay I/O column output data delay I/O control delay I/O register clock-to-output delay I/O combinatorial delay I/O register setup time before clock I/O register hold time after clock I/O register clear delay I/O register feedback delay I/O input pad and buffer to I/O register delay I/O input pad and buffer to row and column delay Output buffer and pad delay, Slow slew rate = off, V CCIO = 5.0 V Output buffer and pad delay, Slow slew rate = off, V CCIO = 3.3 V Output buffer and pad delay, Slow slew rate = on, V CCIO = 5.0 V or 3.3 V Output buffer disable delay Output buffer enable delay, Slow slew rate = off, V CCIO = 5.0 V Output buffer enable delay, Slow slew rate = off, V CCIO = 3.3 V Output buffer enable delay, Slow slew rate = on, V CCIO = 3.3 V or 5.0 V C1 = 35 pF 2.0 1.0 (6)
0.2 0.4 0.5 0.6 0.2 4.0 1.0 1.5 0.0 3.5 1.5 1.8
0.2 0.2 1.0 1.0 1.0 5.0 1.0 3.0 0.0 4.5 2.0 2.5
1.5 1.5 2.0 1.5 1.5
ns ns ns ns ns ns ns
3.0 0.5 5.5 2.5 2.5
ns ns ns ns ns
t OD2
C1 = 35 pF
2.3
3.5
3.5
ns
t OD3
C1 = 35 pF
8.3
10.0
10.5
ns
t XZ t ZX1
C1 = 5 pF C1 = 35 pF
2.5 2.5
2.5 2.5
2.5 2.5
ns ns
t ZX2
C1 = 35 pF
3.0
3.5
3.5
ns
t ZX3
C1 = 35 pF
9.0
10.0
10.5
ns
Altera Corporation
31
MAX 9000 Programmable Logic Device Family Data Sheet
t LOCAL t ROW t COL t DIN_D t DIN_CLK t DIN_CLR t DIN_IOC t DIN_IO
LAB local array delay FastTrack row delay FastTrack column delay Dedicated input data delay Dedicated input clock delay Dedicated input clear delay Dedicated input I/O register clock delay Dedicated input I/O register control delay (6) (6)
0.5 0.9 0.9 4.0 2.7 4.5 2.5 5.5
0.5 1.4 1.7 4.5 3.5 5.0 3.5 6.0
0.5 2.0 3.0 5.0 4.0 5.5 4.5 6.5
ns ns ns ns ns ns ns ns
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Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet
%
EPM9320 EPM9320A EPM9400 EPM9480 EPM9560 EPM9560A
0.81 0.56 0.60 0.68 0.68 0.56
0.33 0.31 0.33 0.29 0.26 0.31
0.056 0.024 0.053 0.064 0.052 0.024
Altera Corporation
33
MAX 9000 Programmable Logic Device Family Data Sheet
1000
1000
800
800
Typical 600 ICC Active (mA)
400
118 MHz
Typical ICC Active (mA)
600
400 144 MHz 42 MHz
200
200 59 MHz
0
25
50
75
100
125
0
25
50
75
100
125
Frequency (MHz)
Frequency (MHz)
1000
1000
800
800
118 MHz
Typical ICC Active (mA)
600 118 MHz
Typical ICC Active (mA)
600
400
400 42 MHz 42 MHz
200
200
0
25
50
75
100
125
0
25
50
75
100
125
Frequency (MHz)
Frequency (MHz)
34
Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet
1000
1000
800
118 MHz
800
Typical ICC Active (mA)
600
Typical ICC Active (mA)
600 144 MHz
400 42 MHz 200
400 59 MHz 200
0
25
50
75
100
125
0
25
50
75
100
125
Frequency (MHz)
Frequency (MHz)
1 ( ( ( ( ) ) 84 ) ) 13 72 43 55 42 30
182 183 153 4 78 49 79 108
V10 U10 V17 W2 A9 D6 C11 A18
AD13 AF14 AD1 AC24 A18 E23 A13 D3
Altera Corporation
35
MAX 9000 Programmable Logic Device Family Data Sheet
6, 18, 24, 25, 48, 14, 20, 24, 31, 35, 61, 67, 70 41, 42, 43, 44, 46, 47, 66, 85, 102, 110, 113, 114, 115, 116, 118, 121, 122, 132, 133, 143, 152, 170, 189, 206 14, 21, 28, 57, 64, 71 15, 37, 60, 79 (3.3 or 5.0 V)
D4, D5, D16, E4, E5, E6, E15, E16, F5, F15, G5, G15, H5, H15, J5, J15, K5, K15, L5, L15, M5, M15, N5, N15, P4, P5, P15, P16, R4, R5, R15, R16, T4, T5, T16
A9, A22, A25, A26, B25, B26, D2, E1, E26, F2, G1, G25, G26, H2, J1, J25, J26, K2, L26, M26, N1, N25, P26, R2, T1, U2, U26, V1, V25, W25, Y26, AA2, AB1, AB26, AC26, AE1, AF1, AF2, AF4, AF7, AF20 D26, F1, H1, K26, N26, P1, U1, W26, AE26, AF25, AF26
(5.0 V only)
10, 19, 30, 45, 112, D15, E8, E10, E12, E14, 128, 139, 148 R7, R9, R11, R13, R14, T14 5, 25, 36, 55, 72, 91, 111, 127, 138, 159, 176, 195 6, 7, 8, 9, 11, 12, 13, 15, 16, 17, 18, 109, 140, 141, 142, 144, 145, 146, 147, 149, 150, 151
D14, E7, E9, E11, E13, R6, A1, A2, A21, B1, B10, B24, R8, R10, R12, T13, T15 D1, H26, K1, M25, R1, V26, AA1, AC25, AF5, AF8, AF19 B6, K19, L2, L4, L18, L19, M1, M2, M3, M4, M16, M17, M18, M19, N1, N2, N3, N4, N16, N17, N18, N19, P1, P2, P3, P17, P18, P19, R1, R2, R3, R17, R18, R19, T1, T2, T3, T17, T18, T19, U1, U2, U3, U17, U18, U19, V1, V2, V19, W1 B4, B5, B6, B7, B8, B9, B11, B12, B13, B14, B15, B16, B18, B19, B20, B21, B22, B23, C4, C23, D4, D23, E4, E22, F4, F23, G4, H4, H23, J23, K4, L4, L23, N4, P4, P23, R3, R26, T2, T3, T4, T5, T22, T23, T24, T25, T26, U3, U4, U5, U22, U23, U24, U25, V2, V3, V4, V5, V22, V23, V24, W1, W2, W3, W4, W5, W22, W23, W24, Y1, Y2, Y3, Y4, Y5, Y22, Y23, Y24, Y25, AA3, AA4, AA5, AA22, AA23, AA24, AA25, AA26, AB2, AB3, AB4, AB5, AB23, AB24, AB25, AC1, AC2, AC23, AD4, AD23, AE4, AE5, AE6, AE7, AE9, AE11, AE12, AE14, AE15, AE16, AE18, AE19, AE20, AE21, AE22, AE23 E25 168
No Connect (N.C.)
29
(4) Total User I/O Pins (5)
56 60
48 132
C4 168
36
Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet
( ( ( ( ) )
) )
2 1 12 74 43 54 42 31 6, 13, 20, 26, 27, 47, 60, 66, 69, 73
182 183 153 4 78 49 79 108 14, 20, 24, 31, 35, 41, 42, 43, 44, 46, 47, 66, 85, 102, 110, 113, 114, 115, 116, 118, 121, 122, 132, 133, 143, 152, 170, 189, 206 10, 19, 30, 45, 112, 128, 139, 148 5, 25, 36, 55, 72, 91, 111, 127, 138, 159, 176, 195 6, 7, 8, 9, 11, 12, 13, 109, 144, 145, 146, 147, 149, 150, 151
210 211 187 234 91 68 92 114 5, 14, 25, 34, 45, 54, 65, 66, 81, 96, 110, 115, 126, 127, 146, 147, 166, 167, 186, 200, 216, 229 4, 24, 44, 64, 117, 137, 157, 177 15, 35, 55, 73, 86, 101, 116, 136, 156, 176, 192, 205, 220, 235 1, 2, 3, 6, 7, 8, 9, 10, 11, 12, 13, 168, 169, 170, 171, 172, 173, 174, 175, 178, 179, 180, 181, 182, 183, 184, 185, 236, 237, 238, 239, 240 67 159
(5.0 V only) (3.3 or 5.0 V)
16, 23, 30, 56, 63, 70 17, 37, 59, 80
No Connect (N.C.)
-
(3) Total User I/O Pins (4)
55 59
48 139
Altera Corporation
37
MAX 9000 Programmable Logic Device Family Data Sheet
( ( ( ( ) )
) )
182 183 153 4 78 49 79 108 14, 20, 24, 31, 35, 41, 42, 43, 44, 46, 47, 66, 85, 102, 110, 113, 114, 115, 116, 118, 121, 122, 132, 133, 143, 152, 170, 189, 206
210 211 187 234 91 68 92 114 5, 14, 25, 34, 45, 54, 65, 66, 81, 96, 110, 115, 126, 127, 146, 147, 166, 167, 186, 200, 216, 229
(5.0 V only) (3.3 or 5.0 V)
10, 19, 30, 45, 112, 128, 4, 24, 44, 64, 117, 137, 139, 148 157, 177 5, 25, 36, 55, 72, 91, 111, 15, 35, 55, 73, 86, 101, 127, 138, 159, 176, 195 116, 136, 156, 176, 192, 205, 220, 235 6, 7, 8, 9, 109, 149, 150, 1, 2, 3, 178, 179, 180, 151 181, 182, 183, 184, 185, 236, 237, 238, 239, 240 48 146 67 175
No Connect (N.C.)
(2) Total User I/O Pins (3)
38
Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet
182 ( ( ( ( ) ) 183 ) ) 153 4 78 49 79 108 14, 20, 24, 31, 35, 41, 42, 43, 44, 46, 47, 66, 85, 102, 110, 113, 114, 115, 116, 118, 121, 122, 132, 133, 143, 152, 170, 189, 206
210 211 187 234 91 68 92 114 5, 14, 25, 34, 45, 54, 65, 66, 81, 96, 110, 115, 126, 127, 146, 147, 166, 167, 186, 200, 216, 229
V10 U10 V17 W2 A9 D6 C11 A18 D4, D5, D16, E4, E5, E6, E15, E16, F5, F15, G5, G15, H5, H15, J5, J15, K5, K15, L5, L15, M5, M15, N5, N15, P4, P5, P15, P16, R4, R5, R15, R16, T4, T5, T16
266 267 237 296 114 85 115 144 13, 22, 33, 42, 53, 62, 73, 74, 102, 121, 138, 155, 166, 167, 186, 187, 206, 207, 226, 254, 273, 290
AD13 AF14 AD1 AC24 A18 E23 A13 D3 A9, A22, A25, A26, B25, B26, D2, E1, E26, F2, G1, G25, G26, H2, J1, J25, J26, K2, L26, M26, N1, N25, P26, R2, T1, U2, U26, V1, V25, W25, Y26, AA2, AB1, AB26, AC26, AE1, AF1, AF2, AF4, AF7, AF20 D26, F1, H1, K26, N26, P1, U1, W26, AE26, AF25, AF26 A1, A2, A21, B1, B10, B24, D1, H26, K1, M25, R1, V26, AA1, AC25, AF5, AF8, AF19
(5.0 V only)
10, 19, 30, 45, 112, 128, 139, 148
4, 24, 44, 64, 117, D15, E8, E10, 12, 32, 52, 72, 137, 157, 177 E12, E14, R7, R9, 157, 177, 197, R11, R13, R14, 217 T14 3, 23, 43, 63, 91, 108, 127, 156, 176, 196, 216, 243, 260, 279
5, 25, 36, 55, 72, 15, 35, 55, 73, 86, D14, E7, E9, E11, (3.3 or 5.0 V) 91, 111, 127, 138, 101, 116, 136, E13, R6, R8, R10, 159, 176, 195 156, 176, 192, R12, T13, T15 205, 220, 235
Altera Corporation
39
MAX 9000 Programmable Logic Device Family Data Sheet
No Connect (N.C.)
109
-
B6, W1
1, 2, 76, 77, 78, 79, 80, 81, 82, 83, 84, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 297, 298, 299, 300, 301, 302, 303, 304
B4, B5, B6, B7, B8, B9, B11, B12, B13, B14, B15, B16, B18, B19, B20, B21, B22, B23, C4, C23, D4, D23, E4, E22, F4, F23, G4, H4, H23, J23, K4, L4, L23, N4, P4, P23, T4, T23, U4, V4, V23, W4, Y4, AA4, AA23, AB4, AB23, AC23, AD4, AD23, AE4, AE5, AE6, AE7, AE9, AE11, AE12, AE14, AE15, AE16, AE18, AE19, AE20, AE21, AE22, AE23 E25 216
(3) Total User I/O Pins (4)
48 153
67 191
C4 216
75 216
40
Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet
Altera Corporation
41
MAX 9000 Programmable Logic Device Family Data Sheet
(R)
42
Printed on Recycled Paper.
Altera Corporation

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